The characteristic that defines ferroelectric is its spontaneous polarization which can be reversed by an electric field. Various ferroelectric materials are known, such as the PZT family of lead zirconate and titanate compounds, Phase III potassium nitride, bismuth titanate or the like, each of which has a Perovskite structure. When the proper electrical field is applied to a ferroelectric material, its polarization is arranged in the same direction. The ferroelectric material retains essentially the same polarization when the electric field is removed. This phenomenon is known as the spontaneous polarization. Because the direction of an applied electric field can change polarizations and the ferroelectric material has two threshold voltages for the reverse of its polarization, it can be thought of as a bistable capacitor.
Referring to FIG. 1, a ferroelectric memory cell MC is shown. The memory cell MC has a cell capacitor C.sub.F and an access transistor Tr acting as a switching device. Capacitor C.sub.F includes an insulating plate made of ferroelectric material used as a capacitor dielectric and two conductive plate electrodes formed on the opposite two surfaces of the plate. One plate electrode of the ferroelectric capacitor C.sub.F is coupled via the source-drain conduction path of the access transistor Tr to a bit line BL, and the other plate electrode of the capacitor C.sub.F is coupled to a plate line PL. The gate electrode of the transistor Tr is coupled to a word line WL.
When a voltage is applied to the ferroelectric plate of the capacitor C.sub.F, the plate is polarized in the direction of the electric field. The switching threshold for changing the polarization state of the ferroelectric capacitor C.sub.F is defined as "coercive voltage". A ferroelectric material has a polarization-voltage characteristic which exhibits hysteresis, and the flow of current to the capacitor C.sub.F depends on its polarization state. If the voltage applied to the capacitor C.sub.F is greater than the coercive voltage, then the capacitor C.sub.F may change polarization states depending on the polarity of the applied voltage. Once polarized by applying a voltage to it in one direction or the opposite direction, the ferroelectric capacitor C.sub.F remains polarized even after the application of the voltage is stopped. Thus, the ferroelectric capacitor C.sub.F can store either logic "one" or logic "zero" in accordance with the state of polarization of the ferroelectric material between two plate electrodes.
FIGS. 2 and 3 illustrate hysteresis curves of polarization of the ferroelectric material in capacitor C.sub.F in accordance with logic states thereof. In each FIG. 2 or 3, the abscissa (or X axis) represents external voltage V applied across the two plate electrodes of the capacitor C.sub.F, and the ordinate (or Y axis) represents polarization P on the ferroelectric material between two plate electrodes. Referring to FIGS. 2 and 3, it will be seen that two stable states exist at points "a" and "e" on the hysteresis curve even when no voltage is applied across the ferroelectric capacitor C.sub.F. This is because the prior history of the voltage applied across the capacitor C.sub.F determines the stable state `a` or `e` which results when voltage is removed. So, the state point `a` can represent logic "1", and the state point `e` can represent logic "0".
As illustrated in FIG. 2, first, it will be assumed that the data "0" is stored in the ferroelectric capacitor C.sub.F whose polarization state at the point `e`. When a voltage of -Ve greater than a coercive voltage of -Vc is applied to one plate electrode of the ferroelectric capacitor C.sub.F, namely, if the voltage of Ve is applied to the plate line PL in a negative direction while the access transistor Tr is conducting, the polarization P is changed from the state point `e` to the state point `d` via the state point `c` and an amount of the charge Q0 stored in the capacitor C.sub.F and corresponding to the state transition is fed out onto bit line BL through the access transistor Tr, resulting in a small voltage change on bit line BL. A resulting voltage change on the bit line BL is detected by a sense amplifier (not shown) connected with the bit line BL. This means that the data of 0 is read from the memory cell MC.
On the other hand, assuming that the data value of 1 is stored in the ferroelectric capacitor C.sub.F whose polarization state at the state point `a`, as illustrated in FIG. 3, in case the voltage -Ve is applied to the plate line PL while the access transistor Tr is conducting, the polarization P is changed from the state point `a` to the state point `d` via state points `b` and `c` and a relatively large amount of the charge Q1 stored in the capacitor C.sub.F and corresponding to the state transition is transferred onto bit line BL via the transistor Tr. A resulting voltage change on the bit line BL is detected by the sense amplifier connected with the bit line BL. This means that the data of 1 is read from the memory cell MC. In this case, however, the polarization P of the capacitor C.sub.F remains at the state point `e` after the application of the voltage -Ve is stopped, that is, the polarization state of the capacitor C.sub.F is changed from the point `a` to the point `e`. After reading the data of 1 from the memory cell MC, thus, the same data "1" on the bit line BL should be written back onto the memory cell MC by lowering the voltage of the plate line PL. This rewrite sequence follows the reverse state transition form the state point `e` to the state point `h` via state points `f` and `g`.
However, if an abrupt voltage is applied to the ferroelectric capacitor C.sub.F during unexpected power down or power off state, there is a possibility that the data stored in the memory cell MC is damaged. More specifically, assuming that the data of 1 is stored in the ferroelectric capacitor C.sub.F whose polarization state is at the point `a` and then the memory device is powered down. During such a power down or off state, if a word line increases in voltage due to the selection of the row decoder, causing the access transistor to be conducting, then the negative voltage -Ve is applied to the ferroelectric capacitor C.sub.F on condition that a voltage of the plate line PL is higher than that of the bit line by the voltage Vc. As a result, the polarization P of the ferroelectric capacitor C.sub.F is shifted from the state point `a` to the state point `d` via state points `b` and `c`. Therefore, after power down, the polarization P settles at the state point `e` corresponding to the data value 0, which means that the contents of the memory cell MC is damaged.
An approach to overcome the above problem is found in U.S. Pat. No. 5,574,679 (Memory Data Protection For A Ferroelectric Memory) issued to Ohtsuki et al., on Nov. 12, 1996. According to the document by Ohtsuki et al., a ferroelectric memory device is provided with a word line selection controller which prevents all the word lines thereof from being selected when the power supply voltage becomes lower than a predetermined threshold voltage level. FIG. 4 illustrates the arrangement of the prior art word line selection controller. Referring to FIG. 4, the word line selection controller 10 includes a row controller 2, an address buffer 4, a row decoder 6, and a memory-cell (MC) protective circuit 8. The row controller 2 controls the input/output operation of the address buffer 4 and the decoding operation of the row decoder 6 based on the row control signal XC. The row address data ADx is retained in the address buffer 4 and then is decoded into a selection signal and nonselection signals by the row decoder 6. That is, the row decoder 6 selects one of the word line WL1-WLn and outputs the selection signal to the selected word line by decoding the row address data ADx stored in the address buffer 4. The MC protective circuit 8 is comprised of n switching transistors STr1-STrn and an inverter circuit IV1. The prior art ferroelectric memory device further includes a power supply voltage detector 12 which checks whether an output voltage of the power supply circuit is lower than a threshold voltage level. If the power supply voltage detector 12 outputs the low-voltage detection signal Vcd to the word line selection controller 10. The switching transistor STr1-STrn are turned on when a high voltage is applied to the gate electrodes thereof. Therefore, when receiving the low-voltage detection signal Vcd from the power supply voltage detector 12, the switching transistors STr1-STrn are simultaneously forced into conduction to set the word lines WL1-WLn at the grounding level independent of the output signals of the row decoder 6, so, thereafter, both the read and write operations of the memory device are prohibited.
However, during a read operation of the data "1", if the memory device is abruptly powered down as soon as the polarization state P of the ferroelectric capacitor C.sub.F is shifted from the point `a` to the point `e` via the points `b`, `c` and `d`, the rewrite operation can not be executed. Consequently, after power down, the polarization P of the capacitor C.sub.F settles still at the point `e`, and thus the data damage of the memory cell MC is inevitable.